Andre Seznec

André Seznec got a PhD in computer sciences from University of Rennes I in France. In 1986, he joined INRIA, the French national research agency in computer science. Apart a sabbatical in industry in 1999-2000, he spent most of his career at INRIA Rennes and was promoted as a Fellow Research Director in 2012.  For the last few years, he has joined industry as an Intel fellow (2021-2024), then a SiFive fellow.

André Seznec has focused his research on processor architecture since the beginning of his Ph.D. thesis in 1983. His early contributions were on vector architectures, particularly the memory system. Since the beginning of 90’s his main research activity has been focused on the architecture of microprocessors, including caches, pipeline, branch predictors, speculative execution, multithreading and multicores. Most members of the microarchitecture research community immediately identify André Seznec as the inventor of the TAGE branch predictor and of the skewed associative cache. His research has influenced the design of many high-end industrial microprocessors, particularly the caches and the branch predictors.

André Seznec has been the leader of compiler and architecture research groups, CAPS then ALF, at INRIA from 1994 to 2016. He has graduated 29 PhD students from 1991 to 2021. He has served as general chair (2010) and PC chair (2016) of the IEEE/ACM ISCA conference. For his work on caches and predictors, he received the Intel Research Impact Medal in 2012, the 2019 Intel Outstanding Researcher award, was promoted as IEEE fellow (2013) and ACM fellow (2016) and received the 2020 B. Rau award.

Read on Seznec's most recent achievements.